The field of the invention is input circuits for industrial digital controllers, and particularly, circuits for interfacing sensing devices such as limit switches, selector switches, solenoids and photoelectric cells with digital equipment such as process controllers, programmable controllers, solid state hardwired controllers and numerical controls.
Industrial digital controllers include a network of logic gates having inputs connected to receive signals from sensing devices such as limit switches, solenoids, photoelectric cells, pushbuttons, etc., and having outputs connected to control the various machine functions in response to the condition of the sensing devices. The logic gates used in such controllers may include AND gates, NAND gates, OR gates, NOR gates and NOT gates. Regardless of the number of gates, the type of gates or their interconnection, they are each responsive to generate either a logic high or a logic low at an output terminal in response to the logic state of their input terminal(s). For example, an AND gate generates a logic high at its output terminal when logic highs are applied to all of its input terminals; otherwise, its output is low.
Logic gates, and digital circuits in general, do not recognize or interpret malfunctions at their input terminals, but instead, interpret them as either a logic high or a logic low. For example, if "current sinking" logic gates are used in a solid state hardwired controller, and an open circuit occurs in the line leading from a limit switch on the machine being controlled, the open circuit will be interpreted as a logic high by the gate which connects to that limit switch. On the other hand, if the line leading from the same limit switch should become shorted to ground, the logic gate may interpret the short circuit as a logic low voltage. Therefore, when such a malfunction occurs the logic gate and associated circuitry respond in a manner not indicated by the sensing device. Also, in such circumstances there is no indication that a malfunction has occurred and the controller continues to operate on erroneous input information.
Means have been proposed for detecting malfunction conditions at the inputs to a logic gate. One such means is the "Fault Detecting and Fault Propagating Logic Gate" disclosed in U.S. Pat. No. 3,743,855 issued to Odo J. Struger on July 3, 1973. Also, control circuits employing such fault mode logic gates have been proposed as disclosed in U.S. Pat. No. 3,751,684, which also issued to Odo J. Struger on Aug. 7, 1973.